Senior Memory Design Engineer

Location: Bengaluru, India

Experience: 5–12 Years

Role Overview

Design, optimize, and verify high-speed, low-power embedded memory compilers and custom memory arrays (SRAM, Register Files, ROM) for advanced process nodes. You will own full-cycle memory architecture, transistor-level circuit design, PPA optimization, and silicon correlation.

Key Responsibilities
Memory Architecture & Design: Architect and design custom SRAM bitcells, sense amplifiers, wordline drivers, precharge circuits, and periphery control logic.
PPA Optimization: Drive power, performance, and area (PPA) trade-offs, leakage reduction, and yield/margin optimization across PVT corners.
Simulation & Verification: Perform transistor-level SPICE simulations, Monte Carlo statistical analysis, aging/reliability checks (EM/IR, BTI/HCI), and functional equivalence verification.
Layout & Physical Design: Guide physical layout teams on floorplanning, matching, DRC/LVS compliance, and post-layout parasitic extraction.
Silicon Bring-Up: Collaborate with characterization, compiler,



and silicon validation teams to debug test-chip failures and correlate silicon data with SPICE models.

Required Qualifications
Experience: 5–12 years of hands-on experience in SRAM/Memory compiler circuit design.
Circuit Expertise: Deep understanding of CMOS transistor physics, bitcell stability (SNM, write margin), sense-amp offset, and low-power design techniques.
EDA Tools: Proficiency in schematic capture and SPICE simulators (Cadence Virtuoso, Spectre, HSPICE, FineSim) and physical verification tools (Calibre).
Scripting: Working knowledge of Python, Tcl, Perl, or SKILL for design automation.
Education: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical Engineering, or VLSI.

Preferred Qualifications
Hands-on tape-out experience in advanced FinFET or GAA (Gate-All-Around) nodes (e.g., TSMC/Samsung 7nm, 5nm, 3nm, 2nm).
Familiarity with memory compiler architecture, liberty (.lib) timing/power modeling, and DFT/MBIST integration.
Robust track record of post-silicon debug and yield enhancement.

📌 Senior Memory Design Engineer Bengaluru
🏢 leadsoc technologies
📍 Bengaluru