Project Role: Functional Verification Engineer
Project Role Description: Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like System Verilog and UVM.
Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.
Must have skills: SoC Verification
Good to have skills : NA
Minimum 5 year(s) of experience is required
Educational Qualification: 15 years full time education
Summary:
As a Functional Verification Engineer, a typical day involves developing and executing comprehensive testbenches to ensure the functional accuracy of digital designs at both block and system levels. The role requires creating a variety of tests, including constrained-random, directed, and coverage-driven scenarios, to thoroughly validate the design.
Collaboration with design and architecture teams is essential to identify potential corner cases and guarantee complete functional coverage prior to tape-out. This position demands a proactive approach to problem-solving and continuous communication across teams to maintain high-quality verification standards throughout the project lifecycle.
Roles & Responsibilities:
- Expected to be an SME,
collaborate and manage the team to perform.
- Responsible for team decisions.
- Engage with multiple teams and contribute on key decisions.
- Provide solutions to problems for their immediate team and across multiple teams.
- Lead efforts to identify verification gaps and propose innovative strategies to enhance test coverage.
- Mentor junior team members to develop their skills and ensure alignment with project goals.
- Coordinate cross-functional reviews to ensure verification completeness and address design concerns.
Professional & Technical Skills:
- Must To Have Skills: Proficiency in SoC Verification.
- Experience with System Verilog and Universal Verification Methodology for creating robust testbenches.
- Robust knowledge of digital design principles and verification methodologies.
- Ability to develop constrained-random, directed, and coverage-driven tests to validate complex designs.
- Familiarity with simulation tools and debugging techniques to analyze verification results.
- Capability to collaborate effectively with design and architecture teams to identify and resolve corner cases.
Additional Information:
- The candidate should have minimum 5 years of experience in SoC Verification.
- This position is based at our Bengaluru office.
- A 15 years full time education is required.