This role offers the opportunity to shape a differentiated verification strategy at the intersection of semiconductor Design Verification SystemC modeling Virtual Platforms and pre-silicon software development.
This leader will define and execute a reuse-first verification strategy spanning SystemC transaction-level models RTL IP subsystem SoC and platform-level validation. The objective is to create a traceable verification asset chain that grows from loosely timed SystemC models through approximately timed models and RTL rather than rebuilding independent verification environments at each stage.
The position is part of Renesas Software First Simulation First engineering organization. The team develops reusable SystemC/TLM models and integrated Virtual Platforms that enable software development verification validation and product evaluation before silicon availability. Design Verification is the quality and release gate that ensures these virtual products faithfully represent the intended silicon behavior.
Key Responsibilities
- Define and drive the verification strategy for SystemC models RTL designs reusable IP subsystems SoCs and Virtual Platforms.
- Lead and develop a global Design Verification organization including verification leads engineers external partners and project-specific teams.
- Establish a common verification architecture that supports reuse of test intent stimulus sequences checkers scoreboards assertions coverage models and regression infrastructure across SystemC and RTL.
- Develop scalable SystemVerilog/UVM environments including protocol adapters and TLM bridges that connect pin-level UVM interfaces to SystemC/TLM models.
- Establish functional-equivalence and timing-correlation methodologies between SystemC LT/AT models and RTL implementations.
- Define common verification plans feature identifiers test intent functional and code coverage goals closure criteria maturity classifications and sign-off requirements.
- Make verification sign-off an explicit release gate for customer- and software-facing Virtual Platform deliveries.
- Drive verification planning and execution from the IP level through subsystem chip-top SoC and full-platform integration.
- Establish a risk-based verification approach that balances reusable UVM environments Python/C tests software-driven validation formal techniques and project schedules.
- Lead verification of configurable and parameterized IP models across supported configurations interfaces and operating modes.
- Build CI/CD-based regression systems for automated compilation simulation coverage collection result analysis release evidence and quality reporting.
- Partner with architecture RTL design SystemC modeling software validation methodology and Product Group teams to define requirements and acceptance criteria.
- Lead complex debug and root-cause analysis across models adapters RTL testbenches firmware and platform-level environments.
- Evaluate and adopt verification technologies that improve quality reuse coverage closure simulation efficiency and engineering productivity.
- Own staffing organizational development program planning partner engagement execution tracking risks dependencies and executive reporting for the DV function.
Leadership Profile
The successful candidate will:
- Set a clear technical and organizational direction while maintaining delivery accountability.
- Balance verification rigor reuse schedule risk and business priorities.
- Build durable methodology without allowing methodology development to block critical product execution.
- Develop strong technical leaders and create clear accountability across IP subsystem SoC and platform verification.
- Promote collaboration across RTL SystemC software validation architecture and product organizations.
- Establish a culture of measurable quality evidence-based sign-off disciplined debug automation and continuous improvement.
Qualifications :
- Bachelors or masters degree in Electrical Engineering Computer Engineering Computer Science or a related field.
- 15 years of experience in semiconductor IP subsystem or SoC Design Verification.
- Demonstrated experience leading geographically distributed verification teams and multiple concurrent programs.
- Deep expertise in SystemVerilog and UVM including verification architecture reusable environments constrained-random testing assertions scoreboards functional coverage and coverage closure.
- Strong knowledge of RTL design and simulation computer architecture embedded processors interconnects memory systems interrupts clocks reset and peripheral interfaces.
- Proven experience defining verification plans and delivering IP or SoC verification through sign-off.
- Experience leading complex debug across RTL testbench firmware interfaces and system-level environments.
- Experience with regression automation verification metrics CI/CD revision control and release-quality governance.
- Strong program-management capabilities including effort estimation staffing schedules priorities risks dependencies and stakeholder communication.
- Strong communication and leadership skills with the ability to influence architects design teams software organizations Product Groups executives and external partners.
Preferred Qualifications
- Experience verifying SystemC/TLM-2.0 models or integrating SystemC models into RTL verification environments.
- Experience creating TLM-to-signal adapters UVM/SystemC bridges DPI interfaces or mixed-language simulation environments.
- Knowledge of SystemC loosely timed and approximately timed modeling functional equivalence timing correlation and performance verification.
- Experience with Python- or C-based verification and running common tests against both SystemC and RTL implementations.
- Familiarity with common SoC protocols and peripheral interfaces such as AMBA AXI/AHB/APB NoC PCIe CXL Ethernet USB SPI I²C/I3C eSPI UART GPIO and memory controllers.
- Experience with formal verification emulation FPGA prototyping software-driven verification or post-silicon validation.
- Experience verifying configurable or parameterized IP and automating configuration-space coverage.
- Familiarity with Virtual Platforms virtual prototyping embedded-software enablement Digital Twin technologies and pre-silicon application validation.
- Experience with commercial simulation debug coverage VIP regression-management and formal-verification tools from providers such as Cadence Synopsys or Siemens EDA.
- Experience building verification teams developing technical leaders managing engineering partners and establishing reusable methodology across multiple projects.
Additional Information :
Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. As the industrys leading expert in embedded processing with unmatched quality and system-level know-how we have evolved to provide scalable and comprehensive semiconductor solutions for automotive industrial infrastructure and IoT industries based on the broadest product portfolio including High Performance Computing Embedded Processing Analog & Connectivity and Power.
With a diverse team of over 21000 professionals in more than 30 countries we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation.
We design and develop sustainable power-efficient solutions today that help people and communities thrive tomorrow To Make Our Lives Easier.
At Renesas you can:
- Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.
- Make a real impact by developing creative products and solutions to meet our global customers evolving needs and help make peoples lives easier safe and secure.
- Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system including the remote work option and Employee Resource Groups will help you excel from the first day.
Are you ready to own your success and make your mark
Join Renesas. Lets Shape the Future together.
Renesas Electronics is an equal opportunity and affirmative action employer committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex race religion national origin gender gender identity gender expression age sexual orientation military status veteran status or any other basis protected by law. For more information please read our Diversity & Inclusion Statement.
Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. With a global team of over 21000 engineers and problem solvers in more than 30 countries we offer the opportunity to work on worldleading technology for Automotive Industrial Infrastructure and IoT shaping a safer healthier greener and smarter future.
At Renesas TAGIE is our culture grounded in being Transparent Agile Global Innovative and Entrepreneurial. It shapes how we work grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.
We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.
Are you ready to join our team and shape the future with us
Renesas Electronics is an equal opportunity and affirmative action employer committed to supporting diversity and fostering a work setting free of discrimination on the basis of sex race religion national origin gender gender identity gender expression age sexual orientation military status veteran status or any other basis protected by law. For more information please read our Diversity & Inclusion Statement.
Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. With a global team of over 21000 engineers and problem solvers in more than 30 countries we offer the opportunity to work on worldleading technology for Automotive Industrial Infrastructure and IoT shaping a safer healthier greener and smarter future.
At Renesas TAGIE is our culture grounded in being Transparent Agile Global Innovative and Entrepreneurial. It shapes how we work grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.
We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.
Are you ready to join our team and shape the future with us
Renesas Electronics is an equal prospect and affirmative action employer committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex race religion national origin gender gender identity gender expression age sexual orientation military status veteran status or any other basis protected by law. For more information please read our Diversity & Inclusion Statement.