Teledyne Technologies Incorporated provides enabling technologies for industrial growth markets that require advanced technology and high reliability. These markets include aerospace and defense factory automation air and water quality environmental monitoring electronics design and development oceanographic research deepwater oil and gas exploration and production medical imaging and pharmaceutical research.
We are looking for individuals who thrive on making an impact and want the excitement of being on a team that wins.
Job Description
Sr. Logic Engineer
Pune Maharashtra India FPGA & High-Speed Protocol Interfaces
ROLE SUMMARY
We are seeking a Staff Logic Engineer to architect implement and deliver complex FPGA-based logic for high-speed protocol analysis and test systems. The role combines hands-on RTL development transceiver and interface integration verification lab debug and technical leadership across PCI Express (PCIe) Compute Express Link (CXL) Ethernet and USB solutions.
About Teledyne LeCroy
Teledyne LeCroy develops high-performance protocol analysis test and measurement solutions used to validate advanced electronic systems. Our engineering teams build hardware and software platforms that help customers bring complex high-speed technologies to market.
What You Will Do
FPGA Architecture and RTL Design
- Own FPGA architecture and microarchitecture for protocol capture packet processing filtering triggering traffic generation timestamping and data movement.
- Design implement and maintain synthesizable RTL using SystemVerilog Verilog or VHDL for high-throughput low-latency datapaths and control logic.
- Integrate and customize FPGA IP for PCIe CXL Ethernet USB DDR memory DMA and other high-speed interfaces.
- Develop robust clocking reset clock-domain crossing and data-path schemes across multiple clock domains and transceiver interfaces.
- Optimize designs for timing closure resource utilization power latency throughput and design maintainability on large FPGAs.
High-Speed Protocol Interface Development
- Develop FPGA logic for complex protocol interfaces such as PCIe CXL Ethernet and USB including packet framing flow control error handling link monitoring and protocol-aware processing.
- Work with high-speed serial transceivers reference clocks equalization controls link-training behavior lane alignment and multi-lane data paths.
- Partner with protocol hardware firmware and software teams to translate specifications and product requirements into implementable FPGA features.
- Analyze protocol traces and lab measurements to identify interoperability performance and corner-case issues.
- Collaborate with verification engineers using SystemVerilog/UVM and coverage-driven methodologies; perform block-level and system-level verification.
- Execute synthesis place-and-route static timing analysis CDC/RDC analysis lint and design-rule checks; resolve implementation and timing issues.
- Debug FPGA hardware using embedded logic analyzers such as Vivado ILA or SignalTap protocol analyzers oscilloscopes and other lab equipment.
- Support board bring-up system integration regression testing issue triage root-cause analysis and release readiness.
Technical Leadership and Collaboration
- Provide technical direction for complex features from concept through production release while remaining deeply hands-on in design and debug.
- Lead architecture and RTL reviews establish coding and verification standards and drive design quality reuse and documentation.
- Mentor engineers in FPGA design timing closure high-speed interfaces protocol behavior and disciplined problem solving.
- Coordinate effectively with cross-functional and geographically distributed teams including product management systems engineering PCB hardware firmware software validation manufacturing and customer support.
- Communicate technical status risks tradeoffs and recommended actions clearly to engineering and program leadership.
Required Qualifications
- Bachelors or Masters degree in Electrical Engineering Electronics Engineering Computer Engineering or a related discipline.
- Typically 8 years of relevant digital design experience with substantial hands-on FPGA development and delivery of production-quality logic.
- Expertise in RTL design with SystemVerilog Verilog or VHDL including synchronous design practices finite-state machines pipelining arbitration buffering and error recovery.
- Demonstrated experience with at least two high-speed protocol families among PCIe CXL Ethernet and USB plus the ability to become effective across the remaining interfaces.
- Strong knowledge of high-speed serial transceivers and FPGA implementation flows on AMD Xilinx UltraScale/Versal or Intel Stratix/Agilex platforms.
- Proven experience with synthesis constraints static timing analysis timing closure CDC/RDC reset architecture and on-chip debug.
- Experience integrating external memory and high-bandwidth data movement including DDR4/DDR5 DMA AXI Avalon or comparable on-chip buses.
- Strong debugging and analytical skills across RTL simulation FPGA implementation board-level behavior and protocol-level observations.
- Ability to create clear architecture documents interface specifications test plans and engineering documentation.
- Effective written and verbal communication skills and the ability to work from the Pune engineering site in a collaborative product-development environment.
Preferred Qualifications
- Deep knowledge of PCIe link and transaction layers LTSSM behavior equalization error handling and protocol analyzer concepts.
- Experience with and familiarity with and concepts coherency-related flows or CXL compliance and interoperability challenges.
- Experience with Ethernet MAC/PCS/FEC datapaths multi-rate designs high-speed SerDes or packet processing pipelines.
- Experience with USB 3.x/USB4 protocol logic Type-C related system considerations or USB protocol analysis and test.
- Background in protocol analyzers traffic generators exercisers compliance tools or other test and measurement products.
- Experience with Python Tcl C/C scripting continuous integration automated regression and source-control workflows such as Git.
- Familiarity with formal verification FPGA prototyping hardware emulation or advanced performance modeling.
- Experience working directly with customers or field teams to resolve complex interoperability and product issues.
- Success in This Role
Deliver scalable FPGA architectures clean RTL predictable timing closure and reliable protocol behavior across demanding high-speed interfaces.
Raise engineering quality through strong reviews mentoring clear decisions practical risk management and effective cross-functional execution.
Work Location
Pune Maharashtra India. The position is intended for close collaboration with local and global engineering teams. Specific work arrangements travel expectations and employment terms will be discussed during the recruiting process.
Teledyne and all of our employees are committed to conducting business with the highest ethical standards. We require all employees to comply with all applicable laws regulations rules and regulatory orders. Our reputation for honesty integrity and high ethics is as significant to us as our reputation for making innovative sensing solutions.
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Required Experience:
Senior IC
📌 Sr. Logic Engineer (Pune)
🏢 Teledyne Technologies
📍 Pune
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