Job Summary

B.Tech / M.Tech in Electrical or Electronics Engineering.
Experince 15 to 20 years
Perform end‑to‑end physical design flow:
Floorplanning
Power planning (PG grid, IR)
Placement & optimization
CTS (Clock Tree Synthesis)
Routing
Post‑route optimization
Achieve timing closure across all modes and corners
Resolve DRC, LVS, ERC and signoff violations
Handle low‑power design techniques:

Key Responsibilities

Multi‑Vt, Multi‑voltage (UPF)
Power gating, clock gating
Perform physical verification and signoff:
STA (Primetime)
SI / Crosstalk
IR drop & EM analysis
Work on advanced nodes (7nm, 5nm, 3nm or below)
Collaborate with:
RTL & Micro‑architecture teams
DFT & Test engineers
Foundry and CAD teams
Debug complex timing, congestion, power, and variability issues
Drive methodology improvements and automation (scripts/flows)

Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.)
Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV

Skill Requirements

Must Have Skill

Physical Design

Valuable to Have Skill

Other Requirements

📌 Senior Technical Architect (Bengaluru)
🏢 HCLTech
📍 Bengaluru