We are looking for skilled DFT Engineers with 2–4 years of hands-on experience in Design for Testability (DFT) implementation for ASIC/SoC designs. The ideal candidate should have practical experience in scan insertion, ATPG, scan compression, and DFT verification, along with a valuable understanding of ASIC design methodologies.
Key Responsibilities
- Implement DFT methodologies for ASIC/SoC designs across the design flow.
- Perform scan insertion, scan chain configuration, and scan compression.
- Develop and execute ATPG patterns to improve manufacturing test coverage.
- Support MBIST, LBIST, and JTAG implementation.
- Perform DFT rule checks (DRC) and resolve design-related violations.
- Debug DFT implementation issues and optimize test coverage.
- Collaborate with RTL Design, Physical Design,
and Verification teams to ensure successful DFT integration.
- Support DFT activities throughout the ASIC design and implementation flow. Required Technical Skills
- 2–4 years of hands-on experience in DFT Design and implementation.
- Strong understanding of Scan Insertion, ATPG, and Scan Compression.
- Knowledge of MBIST, LBIST, and JTAG methodologies.
- Hands-on experience with DFT tools such as:
- Synopsys TestMAX
- Siemens Tessent
- Basic knowledge of Verilog/SystemVerilog.
- Understanding of ASIC/SoC design flow and DFT methodologies.
- Knowledge of Tcl, Python, or Perl scripting will be an added advantage. Work