Role: Physical Design Engineer

Location:
Bangalore & Hyderabad

Experience:
Exp: 4+ yrs NP: 0-15 days joiners Role Summary Seeking an experienced Physical Design Engineer with strong RTL/Netlist-to-GDSII expertise, independent block ownership, and strong root-cause debugging skills.

Key Responsibilities

- Own Physical synthesis, floor planning, placement, CTS, routing, timing closure, and signoff.
- Provide PD feedback on RTL/netlist and resolve implementation issues.
- Debug setup/hold, WNS/TNS, critical paths, clock skew, congestion
- Drive floorplan, macro placement, CTS, clock optimization, and timing convergence.
- Handle MCMM/PVT/RC corners and block/interface timing closure.
- Support EMIR/Power Integrity, LEC/Formal, Physical Verification, and signoff.
- Perform root-cause analysis of PnR and flow issues. Required

Skills:

- Strong Physical Design/PnR and block ownership
- Synthesis and RTL/Netlist understanding
- Floor planning, Placement, CTS, Routing, STA and timing closure
- MCMM/PVT/RC, congestion and interface timing
- EMIR/Power Integrity and LEC/Formal Verification
- Hands-on Fusion Compiler and PrimeTime
- Robust debugging and problem-solving skills

📌 Physical Design Engineer (Bengaluru)
🏢 Softpath Technologies
📍 Bengaluru