14 Nov
|
Tata Elxsi
|
Bengaluru
14 Nov
Tata Elxsi
Bengaluru
## Job highlights
- Strong proficiency in Verilog/SystemVerilog RTL coding and ASIC/FPGA design experience
- Develop and debug digital designs involving FSMs, pipelining, clock-domain crossing, and timing analysis
- Robust proficiency in Verilog/SystemVerilog RTL coding.
- Good understanding of digital design fundamentals, FSMs, pipelining, clock-domain crossing, and timing concepts.
- Experience in ASIC/FPGA design and development flows.
- Knowledge of synthesis, timing analysis, lint, and CDC tools.
- Strong debugging and problem-solving skills.
📌 RTL Design Opportunity (Bengaluru)
🏢 Tata Elxsi
📍 Bengaluru