Job Summary

We are looking for an experienced SoC Verification Engineer with strong expertise in functional verification of complex System-on-Chip (SoC) designs.

The ideal candidate should have hands-on experience in SystemVerilog, UVM, constrained-random verification, functional coverage, and verification of complex IPs and SoC subsystems.

The candidate will be responsible for developing verification environments, creating test plans, executing simulation-based verification, debugging functional issues, and ensuring comprehensive verification coverage. The role involves close collaboration with RTL design, IP verification, architecture, and integration teams to deliver high-quality silicon designs.

Key Responsibilities

- Develop and execute verification plans for complex SoC designs and subsystems.
- Develop and maintain SystemVerilog/UVM-based verification environments and testbenches.
- Create directed and constrained-random test scenarios to validate functional requirements.
- Perform block-level, subsystem-level, and SoC-level functional verification.
- Verify complex IP integrations and interactions between different SoC components.
- Develop UVM agents, drivers, monitors, sequences, scoreboards, and verification components.
- Implement functional coverage models and drive coverage closure.
- Develop and maintain SystemVerilog Assertions (SVA) to validate design protocols and functional behaviour.
- Debug simulation failures, RTL mismatches, and complex integration issues.
- Perform regression testing and analyse simulation results to identify functional defects.
- Verify standard interfaces and protocols such as AMBA AXI, AHB, APB, and other relevant bus protocols.
- Work on clock, reset, interrupt,



power-management, and memory subsystem verification.
- Collaborate with RTL designers to resolve design issues and ensure functional correctness.
- Support gate-level simulation, low-power verification, and post-silicon debug activities wherever required.
- Maintain verification documentation, test plans, coverage reports, and regression results.

Mandatory Technical Skills

- 6+ years of experience in ASIC / SoC Design Verification.
- Strong hands-on experience in SystemVerilog and UVM-based verification.
- Good understanding of digital design concepts, RTL architecture, and SoC design fundamentals.
- Experience developing UVM testbenches and reusable verification components.
- Strong knowledge of constrained-random verification methodologies.
- Experience with functional coverage, code coverage, and coverage closure.
- Hands-on experience with SystemVerilog Assertions (SVA).
- Experience verifying complex IPs, subsystems, and SoC-level integrations.
- Valuable understanding of AMBA protocols, particularly AXI, AHB, and APB.
- Strong debugging skills using simulation waveforms and verification tools.
- Experience with industry-standard simulation tools such as:

- Synopsys VCS
- Cadence Xcelium
- Siemens Questa

- Familiarity with scripting languages such as Python, Perl, or Tcl.

Preferred Skills





- Experience with SoC architecture and integration verification.
- Exposure to multi-core processors, interconnects, memory controllers, DMA, and interrupt controllers.
- Knowledge of cache coherency protocols and memory subsystem verification.
- Experience with low-power verification methodologies, including UPF.
- Understanding of Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) verification.
- Exposure to formal verification and property checking.
- Experience with gate-level simulation and timing-aware verification.
- Knowledge of PCIe, USB, Ethernet, DDR, I2C, SPI, or other high-speed and peripheral interfaces.
- Exposure to emulation platforms and FPGA prototyping.
- Understanding of performance verification, stress testing, and corner-case testing.
- Experience with post-silicon validation and silicon bring-up is an added advantage.

Qualifications

- Bachelor's or Master's degree in Electronics and Communication Engineering, Electrical Engineering, VLSI, or a related discipline.
- Minimum 6+ years of relevant experience in SoC / ASIC Design Verification.
- Strong hands-on experience in SystemVerilog and UVM.
- Ability to independently own verification activities and work with cross-functional engineering teams.
- Key Competencies

- Strong analytical and problem-solving abilities.
- Excellent debugging and root-cause analysis skills.
- Ability to understand complex SoC architectures and identify functional corner cases.
- Strong communication and collaboration skills.
- Ability to manage verification milestones and deliver quality results within project timelines.

📌 Senior SOC Verification Engineer (Hyderabad)
🏢 Hucon Solutions
📍 Hyderabad