Job highlights

- Masters/ Bachelors in EE / EC/CS with 10+ years of experience in IP / ASIC Verification. Should have experience in managing the teams for at least 3 years.

1) Verification Lead - IP, UVM, System Verilog - [ID 017]

Masters/ Bachelors in EE/EC/CS with 10+ years of experience in IP/ASIC Verification.

Should have experience in managing the teams for at least 3 years.

Leadership skills demonstrated as a part of the team.

Should have extensively worked on x86 or any other complex architecture.

Should have extensive knowledge in assembly programming ,parallel programming and ULT development using UVM/SV

Knowledge of working in Emulation platform and Prototyping in platforms like palladium, zebu.

Skills:

IP, Verification, UVM, System Verilog

Job Location:

Hyderabad

Experience:

10 - 15 Years

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Verification Lead IP, UVM, System Verilog (Hyderabad)
🏢 Vitestork Consulting
📍 Hyderabad