Job highlights

- Minimum 7 years of experience in System Verilog HVL.
- Minimum 7 year of experience in OVM / UVM/VMM / Test Harness.
- Hands on experience of developing assertion,checkers,coverage and scenario creation. Must have executed at-least 2 to 3 SoC Verification projects
- Experience in developing test and coverage plan,Verification setting and validation plan.

1) Technical Lead- Design Verification - [ID 018]

Minimum 7 years of experience in System Verilog HVL.

Minimum 7 year of experience in OVM/UVM/VMM/Test Harness.

Hands on experience of developing assertion, checkers, coverage and scenario creation.

Must have executed at-least 2 to 3 SoC Verification projects

Experience in developing test and coverage plan, Verification environment and validation plan.

Knowledge of at-least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required.

Review and Audit participation.





At-least 1 years of experience in handling team of 4 to 6 engineers.

Define/derive Scope, Estimation, Schedule and Deliverables of proposed work.

Assure compatibility of resources, tools, platform

Work with customers through acceptance of deliverables.

Effectively manage team members through coaching and mentoring and provide guidance and career planni

Skills:

SV , UVM , OVM, PCIe, NVMe

Job Location:

Hyderabad

Experience:

7 - 15 Years

Company Name:

Well Established Semiconductor Services

Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

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