- Should have good understanding of verilog / VHDL
- Knowledge of tcl and perl scripting is a must
1) Synthesis / STA Engineers & Experts - [ID 018]
Expert in developing chip constraints working with RTL and DFT teams
Synthesis and STA Expertise with synopsys/Cadence tools
Knowledge of Netlist to GDSII flow
Should have positive understanding of verilog/VHDL
Exposure to low power techniques
Knowledge of tcl and perl scripting is a must
Block Level Synthesis
SOC Synthesis
Skills:
STA, Synthesis, SOC
Job Location:
Bangalore | Noida
Experience:
5 - 15 Years
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