- 7-15 years experience in static timing analysis with proficiency in Synopsys PrimeTime or Cadence Tempus and scripting skills in Perl, Python, or Tcl
- Perform static timing analysis, timing optimization, and collaborate across RTL design, synthesis, and physical design flows
7-15 years of experience in static timing analysis for digital IC design. Strong understanding of digital design concepts, including flip-flops, latches, combinational logic, and clocking methodologies.
Proficiency in using STA tools like Synopsys PrimeTime, Cadence Tempus, or similar tools.
Experience with timing optimization techniques and methodologies.
Knowledge of various design flows, including RTL design, synthesis, and physical design.
Familiarity with scripting languages such as Perl, Python, or Tcl for automation of STA tasks.
Solid analytical and problem-solving skills with attention to detail.
Excellent communication skills to collaborate effectively with cross-functional teams.