Job highlights

- Experience in processor design - RISC / DSP/VLIW / SIMD architectures and / or memory subsystem design,cache hierarchy design.
- Experience of multi-million gate ASIC design and verification methodologies
- Experience in AMBA AXI,AHB,and APB protocols
- Experience in logic design with Verilog and / or System Verilog and validation / verification

1) Staff Design Engineer_ASIC Design (Subsytems) - [ID 017]

Capability to understand a given block specification and come up with Micro Architecture

Capability to derive an architecture and micro architecture based on a given algorithm

Experience in processor design - RISC/DSP/VLIW/SIMD architectures and/or memory subsystem design, cache hierarchy design.

Knowledge in digital logic for HW safety/protection - ECC, Parity, WDT etc.





Experience of multi-million gate ASIC design and verification methodologies

Knowledge of Computer architecture

Experience in AMBA AXI, AHB, and APB protocols

Expertise in System on Chips.

Knowledge of digital design methodologies and tool flow

Excellent logic design, debugging and problem-solving skills.

Experience in logic design with Verilog and/or System Verilog and validation/verification

Experience in lint checks, area optimization, power optimization, GLS, synthesis and timing analy

Skills:

RTL ASIC Design, Micro Architecture

Job Location:

Hyderabad

Experience:

8 - 12 Years

📌 Staff Design Engineer_ASIC Design (Subsytems) (Hyderabad)
🏢 Vitestork Consulting
📍 Hyderabad