Job highlights

- 3+ years experience with solid expertise in Synthesis & Timing concepts, .lib formats (NLDM, CCSM, ECSM), DC-topo tools, and STA; BTECH/MTECH in EEE/ECE/CS or equivalent
- Perform pre and post layout Static Timing Analysis, handle block and top-level timing closure, manage clocking structures, budgeting, and hierarchical designs, and apply basic Formal verification and Spyglass knowledge

Mirafra Technologies is hiring STA Engineers.

Experience : 3+ years

Location: Bangalore

Notice Period : Immediate to 30 days

:

- Should be very strong in Synthesis & Timing concepts
- Should understand .lib very well. Should be aware of all types of libs like NLDM, CCSM, ECSM etc.
- Should have knowledge of DC-topo of similar concepts in other tools (RTL Compiler, talus)
- Timing basics should be very strong
- Should understand the clocking structures and concepts very well.
- Should have handled both block and top level. Should know the concepts of budgeting other techniques to handle hierarchical designs
- Should have done both pre and post layout STA
- Should have basic knowledge of Formal verification, Spyglass

Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

📌 Sta Engineer (Bengaluru)
🏢 Mirafra
📍 Bengaluru