Job highlights

- Required Qualifications: Solid background in functional verification fundamentals.
- Prior digital verification experience in serial bus multiprotocol PHY IPs (UCIE or SerDes IPs is preferred)
- Experience in: Verification environment development

1) Sr Principal Design Engineer / Lead - Verification (DDR / PHY / UCIE) - [ID 017]

Lead Design Verification (DV) execution of UCIe PHY IP.

Drive internal DV team meeting for day to day execution. Work closely with RTL, AMS system modelling and PD teams.

Lead technical alignment on verification strategies. Define and architect verification environments and methodologies.

Take initiative to drive overall execution efficiency and quality improvements.

Required Qualifications

Solid background in functional verification fundamentals.

Experience in: Verification workplace development

Test plan creation

Verification closure

RTL and GLS debug skills, formal verification, PA simulation

Strong System Verilog and UVM methodology expertise.

Prior digital verification experience in serial bus multiprotocol PHY IPs (UCIE or SerDes IPs is preferred).

Skills:

DDR, PHY, UCIE,

Job Location:

Bengaluru

Experience:

8 -15 Yrs

📌 Sr Principal Design Engineer / Lead - Verification (Bengaluru)
🏢 Vitestork Consulting
📍 Bengaluru