Job highlights

- Required Qualifications: Solid background in functional verification fundamental

1) Sr Principal Design Engineer/Lead- UCIE PHY (IP, TestChip, MPML) Verification - [ID 018]

Key Responsibilities

Lead Design Verification (DV) execution of UCIe PHY IP.

Drive internal DV team meeting for day to day execution. Work closely with RTL, AMS system modelling and PD teams.

Lead technical alignment on verification strategies. Define and architect verification environments and methodologies.

Take initiative to drive overall execution efficiency and quality improvements.

Improve and evolve existing verification methodologies : Co-Simulation (Co-SIM), UPF Power Aware Simulations (UPF PA Sim), VIP/DIP integration and Verification, increase Formal Verification usage especially FPV, Safety Verification Analyze execution and quality issues to define, develop, and deploy current functional verification methodologies for continuous improvement.

Required Qualifications: Solid background in functional verification fundamental

Skills:

UCIE PHY (IP, TestChip, MPML) Verification

Job Location:

Bengaluru

Experience:

10 - 16 Yrs

📌 Sr Principal Design Engineer/Lead- UCIE PHY (Bengaluru)
🏢 Vitestork Consulting
📍 Bengaluru