- Work experience with node 5nm or lower node designs with advanced low power techniques is must.
- Experience on ASIC Physical Design: Floorplanning,P&R;,extraction,IR Drop Analysis,Timing and Signal Integrity closure,Physical Verification are essential part of the job. Well versed with Cadence or Synopsys tools is important.
1) Senior Engineer_ Physical Design - [ID 018]
Work experience with node 5nm or lower node designs with advanced low power techniques is must.
Experience on ASIC Physical Design: Floorplanning, P&R;, extraction, IR Drop Analysis, Timing and Signal Integrity closure, Physical Verification are essential part of the job.
Well versed with Cadence or Synopsys tools is important.
Experience with Static Timing Analysis in Primetime or Primetime-SI is important.
Hands-on experience in scripting languages such as PERL, TCL is important.
Implement robust clock distribution solutions using appropriate methods that meet design requirements.
Make valuable independent technical trade-offs between power, area, and timing (PPA).
Interact with Design team to help drive and resolve design issues related to PnR closure.
Timing closure on high-speed interfaces is a plus.
Knowledge on Full chip Physical Design is beneficial.
Good ASIC fun
Skills:
ASIC Physical Design, Innovus
Job Location:
Noida
Experience:
4 - 8 Years
Company Name:
Well Established Semiconductor Services
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