WE ARE HIRING | Senior DFT Engineer

Location: Bangalore

Experience: 7 Years

Open Positions: 2

Notice Period: Immediate to 30 Days Only

We are looking for experienced Senior DFT Engineers with strong hands-on expertise in Design for Testability (DFT) for complex ASIC/SoC designs.

Key Responsibilities

- Develop and implement DFT architectures for ASIC/SoC designs.
- Perform scan insertion, scan stitching (flat and hierarchical) and scan compression.
- Generate ATPG patterns, perform fault simulation and improve test coverage.
- Implement MBIST/LBIST architectures.
- Integrate JTAG and Boundary Scan.
- Work on IEEE 1500 and IEEE 1687 (iJTAG) wrapper integration.
- Perform DFT timing analysis and manage scan timing constraints.
- Collaborate with RTL, Physical Design and Silicon Validation teams.
- Support ATE pattern generation, validation and silicon bring-up.

Required Technical Skills

- Synopsys DFT Compiler




- Synopsys TetraMAX
- Siemens EDA / Mentor Tessent
- Scan Insertion & ATPG
- MBIST / LBIST
- JTAG / Boundary Scan
- Verilog / VHDL
- Tcl / Python scripting
- Basic STA and timing constraints knowledge

Mandatory Requirements

- 7 years of relevant hands-on DFT experience.
- Robust ASIC/SoC DFT implementation background.
- Practical experience in Scan Insertion and ATPG.
- Hands-on experience with Tessent or Synopsys DFT tools.
- Candidates with an immediate to 30-day notice period only.

Interested candidates: Please share your updated resume at: [HIDDEN TEXT]

#Hiring #DFT #SeniorDFTEngineer #ASIC #SoC #VLSI #ScanInsertion #ATPG #Tessent #MBIST #LBIST #SemiconductorJobs #BangaloreJobs #DesignForTestability

📌 Senior Engineer (Bengaluru)
🏢 Canvendor
📍 Bengaluru