About the Company www.enchargeai.com

About the Role

RAS Architect – Reliability, Availability & Serviceability

Location: Onsite/hybrid/Remote

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EnCharge AI is seeking an architect with deep expertise in Reliability, Availability, and Serviceability (RAS) to help architect the next-generation AI inference platform, from the SoC through scale-up and scale-out clusters. You will own the RAS architecture end to end, ensuring that errors are detected, contained, reported, and recovered from at every level, from on-chip memory to the rack, so that datacenter-scale inference deployments meet their availability and data-integrity targets.

This role focuses on defining and integrating RAS features such as ECC and error handling across SRAM, HBM/DRAM, and on-chip interconnect , error containment and poison propagation

, scale-up and scale-out fabric resilience , silent data corruption (SDC) detection , and telemetry-driven fault management at the hardware, firmware, and system software layers.

You will define and drive architectural specifications for PCIe/CXL error reporting and recovery, link retry and lane degradation, BMC/Redfish-based health monitoring, and job-level recovery for large inference clusters, backed by quantitative FIT, MTBF, and availability models.

Responsibilities:

- Define the SoC- and system-level RAS architecture, including error classification (corrected, uncorrected-recoverable, fatal), detection, containment, logging, and reporting flows from IP to host and BMC.
- Architect ECC and error-handling schemes for on-chip SRAM and compute arrays, HBM/DRAM (on-die and link ECC, scrubbing, page retirement, and sparing), and the on-chip interconnect, including data poisoning and poison propagation across the memory and fabric hierarchy.
- Define RAS for host and peer interfaces, including PCIe/CXL AER,



Downstream Port Containment (DPC), hot-plug and surprise removal, and function-level reset and recovery.
- Architect resilience for scale-up (NVLink/UALink-style) and scale-out (Ethernet/UEC, RDMA) fabrics , including link-level retry, CRC/FEC monitoring, lane degradation, path failover, and graceful handling of link and node loss.
- Drive the silent data corruption strategy: end-to-end data integrity protection, in-field self-test and fleet screening, and detection of marginal or degrading silicon.
- Build and maintain FIT, MTBF, and availability models from component to cluster level; set RAS targets and translate them into requirements for IP, package, board, and system.
- Define telemetry, health monitoring, and predictive-failure capabilities, including error counters, thresholds, and sensor data exposed through BMC/OpenBMC and Redfish and aligned with OCP fault management.
- Define firmware recovery, field diagnostics, and serviceability flows, including error-driven resets, component isolation, field-replaceable unit (FRU) identification, and RMA and failure-analysis feedback loops.
- Collaborate with firmware, system software, and ML runtime teams on job-level resiliency for large inference deployments, including fault notification, request re-routing, checkpoint/restart of stateful workloads, and degraded-mode operation.
- Define the RAS verification plan, including pre-silicon and post-silicon error-injection infrastructure,



and participate in silicon bring-up and validation of RAS features.
- Serve as the technical authority for RAS across architecture, silicon, firmware, and system teams; drive cross-functional RAS reviews and trade-offs and mentor engineers on reliability design.
- Ensure alignment with industry standards and best practices (e.g., JEDEC, PCIe/CXL, OCP, DMTF Redfish).

Required Background:

- BS/MS/Ph.D. in EE, CE, CS, or related field with 10+ years of SoC, server, or datacenter system architecture experience, including 6+ years focused on RAS.
- Deep knowledge of error detection and correction (parity, SECDED, symbol-based/Chipkill-class ECC, CRC) and memory RAS for HBM and DDR/LPDDR.
- Solid understanding of error containment, poison propagation, and error-reporting architectures (e.g., x86 MCA, Arm RAS Extension, RISC-V RERI).
- Experience with PCIe RAS (AER, DPC, hot-plug) and high-speed link resilience (retry, FEC, lane degradation) in fabrics such as NVLink, UALink, Ethernet/UEC, or RoCE.
- Hands-on experience with reliability modeling (FIT, MTBF, availability) and with soft-error, aging, and SDC mechanisms in advanced process nodes.
- Familiarity with BMC/OpenBMC, Redfish, PLDM/MCTP, OCP fault management, fleet telemetry, and field diagnostics/RMA processes.
- Experience taking RAS features through silicon bring-up and into production deployment at datacenter scale.
- Proven technical leadership: defining architecture across multiple teams and influencing product and roadmap decisions as a senior individual contributor.
- Experience with large-scale AI cluster resiliency, RISC-V SoCs, or SystemVerilog/UVM-based error-injection verification a plus.

Contact

- Contact: Uday
- Mulya Technologies
- [email protected]
- www.mulyatech.com

📌 RAS Architect – Reliability, Availability & Serviceability (India)
🏢 EnCharge AI
📍 India