Job highlights

- Requirements: B Tech /BE / ME/M Tech with 8-15+ years of relevant hands-on experience in Design for Test (DFT). Clear understanding of key DFT concepts like Scan compression,Scan Stitching,fault models (stuck-at,delay tests,IDDQ,Small Delay,etc.)

1) Principal / Sr. Principal Design Engineer - DFT - [ID 017]

Define the DFT Architecture for the next generation SoCs.

Implementation verification including Scan, PMBIST, JTAG and other DFT s related logic.

Define and develop methodology for DFT insertion, pattern development, manufacturing tests, verifications, etc

Working closely with cross functional teams to develop and verify DFT s structures and constraints.

Perform RTL and gate level (no-timing and timing) simulations to verify DFT functionality.

Work closely with Test Engineering for test program development and Silicon bring up, diagnosis, Yield improvement, etc.





Work closely with EDA RnD teams to propose and implement new features.

Requirements

B. Tech /BE/ME/M Tech with 8-15+ years of relevant hands-on experience in Design for Test (DFT).

Transparent understanding of key DFT concepts like Scan compression, Scan Stitching, fault models (stuck-at, delay tests, IDDQ, Small Delay, etc.)

Skills:

SCAN, PMBIST, JTAG

Job Location:

Bengaluru

Experience:

12 - 18 Years

Company Name:

Semiconductor RD

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📌 Principal / Sr. Principal Design Engineer - DFT (Bengaluru)
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