Job highlights

- Proficient in Verilog coding and RTL design,data path designs,
- Requirement: the Candidate is expected to have a good understanding of the digital design flow. Proficient in Verilog coding .
- Experience in writing Verilog testbench and running simulations. Desired Protocols knowledge - USB,PCIe,MIPI(DPHY),HDMI / Display

1) Principal RTL Design Engineer - [ID 017]

1. Proficient in Verilog coding and RTL design, data path designs,
2. Knowledge of RTL checks ex- LINT, SDC, CDC
3. Familiar with synthesis flow and timing constraints
4. Experience in writing Verilog testbench and running simulations.
5. Desired Protocols knowledge - USB, PCIe, MIPI(DPHY), HDMI/Display Nature of work:



The Candidate will be responsible for the design and implementation of high-speed SerDes PHY at the cutting edge nodes.

Responsibilities include the architecture of high-speed SerDes IP, design, lint, synthesis, static timing analysis, DFT, formal verification, at block, core, and chip levels.

Work closely with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuits

Requirement: the Candidate is expected to have a valuable understanding of the digital design flow.

Proficient in Verilog coding

Skills: RTL, LINT, CDC, Serdes Phy

Job Location:

Bengaluru

Experience:

8 - 15 Years

📌 Principal RTL Design Engineer (Bengaluru)
🏢 Vitestork Consulting
📍 Bengaluru