1) Principal Engineer - FPGA/ASIC, RTL Design - [ID 017]

Responsibilities

Excellent Leading communication skills and demonstrate the desire to take on diverse challenges.

Experienced with large FPGA development flow and tools on Xilinx devices.

Experience in wireless communication

Proficient in Verilog RTL language. Experienced with large FPGA development on Xilinx devices.

Very familiar with Xilinxs build flow including design entry in Verilog, synthesis, place and route, timing constraints and timing closure.

Hands on with lab FPGA debug methodologies.

Hands on experience with lab debug equipment, such as oscilloscopes and logic analysers.

Experience with verification methodologies, RTL and gate level simulations and debug.





Experience debugging silicon and PCB issues.

Run basic verification tests (on simulations)

Minimum Qualifications

BSc/ MSc in Electr

Skills:

FPGA Design, RTL, ASIC Design

Job Location:

Hyderabad

Experience:

10+ Years

Company Name:

Startup RD - Telecommunication Semiconductors

Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Principal Engineer - FPGA/ASIC, RTL Design - [ID 017] (Hyderabad)
🏢 Vitestork Consulting
📍 Hyderabad