About the Company www.enchargeai.com

About the Role

Locations: Bangalore (Hybrid-2 days office/3 days Home)/ Remote ( Any where in India ) Memory Sub-System Architect – AI Inference Systems Location: Onsite/hybrid/Remote : EnCharge AI is seeking an experienced Principal/Distinguished Memory Architect with deep expertise in DRAM and advanced memory integration to help architect the next-generation datacenter AI inference platform, from a single accelerator to rack- and cluster-scale deployments. As the technical lead for the memory subsystem, you will own the memory architecture around EnCharge's in-memory compute arrays, determining how much model, context, and concurrency each accelerator can serve and how efficiently off-chip and stacked memory keep those arrays fed for production generative AI workloads. This role focuses on defining the memory technology, controller, and PHY architecture across LPDDR5/5X/6 and HBM3/3E/HBM4, including custom HBM base die, and on integrating 3D-stacked memory through hybrid bonding and advanced chiplet packaging.

You will translate LLM inference behavior (weight streaming, KV-cache capacity and bandwidth, batching, and context length) into memory requirements, define the hierarchy from the in-memory compute arrays and on-die SRAM through HBM, LPDDR, and CXL-attached pooled memory, and work closely with performance, RAS, packaging, and silicon teams, as well as leading DRAM vendors, to turn those requirements into architecture specifications.

Responsibilities

- Own the memory subsystem architecture for AI inference accelerators and systems, defining memory technology choices, configurations, and roadmap across LPDDR5/5X/6, HBM3/3E/HBM4, and 3D-stacked memory, balancing bandwidth, capacity, latency, power, cost, and supply.
- Partner with the performance team to build and correlate memory models, from analytical bandwidth/capacity models to DRAM timing-accurate simulation of bank, channel, refresh, and scheduling effects,



and use them to drive architecture decisions.
- Architect memory controllers and PHY requirements, including command scheduling, page policy, address mapping and interleaving, refresh management, QoS across many requestors, low-power states, PHY training, data rates, and die-edge (beachfront) and area budgets.
- Evaluate and architect 3D-stacked memory, including hybrid-bonded SRAM and DRAM stacking, logic-on-memory and memory-on-logic configurations, and chiplet integration via UCIe and 2.5D/3D packaging (CoWoS), assessing bandwidth density, energy per bit, yield, cost, and known-good-die strategy.
- Work with package, thermal, and power-integrity teams on the implications of stacking, including DRAM temperature limits and refresh derating, logic hot spots under memory, TSV-based power delivery, IR drop, and stack height and power envelopes.
- In coordination with the RAS architect, define memory RAS features, including ECC (on-die, link, and system-level), scrubbing, error logging, row and column repair and post-package repair, page retirement, and RowHammer mitigation.
- Serve as the technical lead for memory vendor engagement with leading memory vendors covering roadmaps, custom features, samples, and qualification, and influence device specifications to fit inference workloads.
- Track and contribute to JEDEC memory standards and related CXL and UCIe specifications, and represent the company in standards bodies where appropriate.
- Define memory validation, characterization, and bring-up plans (training, margining, and stress), correlate models against silicon,



and participate in silicon and system bring-up.

Qualifications

- BS/MS/Ph.D. in EE, CE, CS, or related field with deep experience architecting memory subsystems for SoCs, accelerators, GPUs, or servers.

Required Skills

- Deep knowledge of DRAM device architecture and operation (banks, bank groups, pseudo-channels, timing parameters, refresh, and page policy) and of the LPDDR5/5X and HBM3/3E standards, with familiarity with LPDDR6 and HBM4.
- Familiarity with JEDEC memory standards and the standardization process; active participation in JEDEC committees (e.g., JC-42 for DRAM, JC-16 for interfaces) a strong plus.
- Hands-on experience with memory controller and PHY architecture, including scheduling, QoS, address mapping, training, power management, and signal- and power-integrity considerations at high data rates.
- Strong understanding of advanced packaging and 3D integration, including 2.5D interposers and bridges, hybrid bonding and 3D stacking, TSVs, and UCIe chiplet interfaces, and their thermal and power-delivery implications.
- Working knowledge of memory RAS, including SECDED and symbol-based ECC, on-die ECC, scrubbing, post-package repair, and RowHammer mitigations.
- Experience working directly with DRAM vendors and foundry partners and taking memory subsystems through silicon bring-up into production.
- Proven technical leadership: defining architecture across multiple teams and influencing product and roadmap decisions as a senior individual contributor, with robust written and verbal communication skills.

Preferred Skills

- Experience with custom HBM base die design, near-memory or in-memory compute, or a DRAM device or process background a plus.

Pay range and compensation package

Not specified.

Equal Opportunity Statement

Not specified.

Contact

- Contact: Uday
- Mulya Technologies
- [HIDDEN TEXT]
- - www.mulyatech.com

📌 Memory Sub-System Architect AI Inference Systems (India)
🏢 EnCharge AI
📍 India