Job highlights

- Experience in wireless communication,Proficient in Verilog RTL language
- Hands on experience with lab debug equipment,such as oscilloscopes and logic analysers
- Experience with verification methodologies,RTL and gate level simulations and debug
- Experience debugging silicon and PCB issues

1) Manager / Sr. Manager - FPGA RTL Design (DSP/Wireless) - [ID 017]

Excellent Leading & communication skills and demonstrate the desire to take on diverse challenges. Experienced with large FPGA development flow and tools on Xilinx devices. Experience in wireless communication, Proficient in Verilog RTL language. Experienced with large FPGA development on Xilinx devices. Very familiar with Xilinxs build flow including design entry in Verilog, synthesis, place and route, timing constraints and timing closure.





Hands on with lab FPGA debug methodologies. Hands on experience with lab debug equipment, such as oscilloscopes and logic analysers. Experience with verification methodologies, RTL and gate level simulations and debug. Experience debugging silicon and PCB issues. Run basic verification tests (on simulations)

Skills:

FPGA, RTL Design,DSP/Wireless

Job Location:

Hyderabad

Experience:

15 - 19 Years

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Manager / Sr. Manager FPGA RTL Design (DSP/Wireless) (Hyderabad)
🏢 Vitestork Consulting
📍 Hyderabad