- Masters in Electronics Engineering (a relevant experience with minimum 4 years in a semiconductor or high technology RD environment would be appreciated)
- Experience in Hardware Design Language (such as VHDL or Verilog).
- Experience in Digital verification with various skill sets: (a) Universal Verification Methodology (UVM)
(b) System Verilog (SV)
(c) C/C++ language, preferably with ARM CORTEX processor
(d) Formal Methodology (Jasper GOLD)
(e) Scripting languages (PERL, TCL, PYTHON)
- Good communication and written skills in English.
- Able to work in a multi-cultural team.
- Solid analytical and problem-solving skill. -Able to keep up with fast moving new verification methodology.
Skills: UVM, SV, C / C++, ARM Processors
Experience:
7 - 12 years
📌 Lead Digital Verification Engineer - SOC (Bengaluru)
🏢 Vitestork Consulting
📍 Bengaluru
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