Job highlights

- Prior RTL Design experience using Verilog is a must - so that the verification engineer is self-sufficient for most aspects of debugging. HBM4 Protocol experience is highly desirable
- Prior experience in functional verification and debugging of complex protocols is a must. AXI3 / 4 experience is a desirable.
- Prior experience in IP development te

1) Lead Design Engineer - [ID 018]

Bachelor s/Master s degree in Electronics or Equivalent engineering stream.

5 to 8 years of Design verification experience with a large portion of the recent work experience on verification environment development.

Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.

Should have knowledge on all aspects of verification components & verification metrics.





System Verilog experience and experience with UVM based functional verification workplace development is mandatory.

Prior RTL Design experience using Verilog is a must - so that the verification engineer is self-sufficient for most aspects of debugging.

HBM4 Protocol experience is highly desirable. Prior experience in functional verification and debugging of complex protocols is a must.

AXI3/4 experience is a desirable.

Prior experience in IP development te

Skills:

Functional Verification, DDR, PHY, SV , UVM

Job Location:

Bengaluru

Experience:

5 - 8 Years

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Lead Design Engineer (Bengaluru)
🏢 Vitestork Consulting
📍 Bengaluru