Required Qualification

- Experience with in Block, Sub-Systems and SOC level verification

- Should possess solid knowledge of formal verification and methodologies

- Experience in handling Property, Coverage, Sequential, Register, Connectivity verification apps

- Experience in architecting the FV testbench, plan properties, constraints and coverage for complex designs and getting closure with formal core.

- Preferred to have knowledge in scripting language (Python) and ability work with AI enabled environments for generating properties, constraints and coverage as well as reviewing the AI generated testbenches and properties.

- Experience in debugging the end-to-end properties as well as complex protocols checking failures and root causing the failure.

- Should be familiar with abstract modelling and other convergence techniques

- Work with design and/or verification lead for ensuring verification plan is complete and closure is assured.

- 4+ years of experience in working on complex designs like CPU, GPU, RISC V, end point IPs, NOCs,



complex arbiters etc

Technical Skills

- Should understand of digital design fundamentals and RTL development.

- Proficiency in Verilog, System Verilog

- Strong understanding with Jasper Gold or VC Formal tools commands and tool flows

- Experience with commercial simulators (VCS, Xcelium) and debug platforms (Verdi, Verisium)

- Good understanding of System Verilog/UVM testbenches

- Robust understanding of SoC architecture and bus protocols

- Serial protocols like I2C, I2S, UART etc

- ARM bus protocols like APB, AHB, AXI, CHI etc

- Any one of the high-speed protocols like PCI gen6+, USB3+, Gigabit Ethernet, UCIe

- Memory standards- Flash, NVMe, DDRs, LPDDRs (Preferred)

Soft Skills

- Strong analytical and problem-solving skills.

- Excellent debugging capability.

- Ability to work independently and in cross-functional teams.

- Strong ownership and delivery mindset.

📌 Formal Verification Engineer (Bengaluru)
🏢 Blueberry Semiconductors
📍 Bengaluru