We are seeking a highly skilled Design Verification Engineer with 6+ years of experience, specializing in building and enhancing testbenches for complex digital designs. The ideal candidate will have robust expertise in verification methodologies, testbench architecture, and debugging, with hands-on experience in UVM-based environments.
Required Skills:
- Strong hands-on experience in testbench development (UVM preferred).
- Proficient in SystemVerilog, UVM/OVM/VMM methodologies.
- Strong debugging skills using tools like VCS, Questa, or Xcelium.
- Good understanding of digital design concepts (RTL, clocking, resets, FIFOs, DMA, etc.).
- Experience in writing assertions (SVA) and functional coverage.
- Familiarity with scripting languages (Python, Perl, Shell, etc.) for automation.
- Strong analytical and problem-solving skills.
📌 DV Engineer (Bengaluru)
🏢 Proxelera
📍 Bengaluru
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