Job highlights

- Collaborate with RTL,verification,physical design,and silicon teams. Must-Have Skills: 7 10 years of hands-on experience in SoC DFT. Strong expertise in Scan,ATPG,MBIST.
- Experience with pre-silicon validation and post-silicon debug. Strong problem-solving and debugging skills. Ability to work effectively in a cross-functional engineering setting

1) DFT Engineer - SoC-level DFT architecture - [ID 017]

Key Responsibilities: Define and implement SoC-level DFT architecture for large and complex designs.

Develop, integrate, and support Scan ATPG, MBIST, BSCAN, and IJTAG.

Perform DFT insertion, verification, and coverage analysis at block and SoC levels.

Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.

Support post-silicon debug, failure analysis, and yield learning.

Collaborate with RTL, verification, physical design, and silicon teams.





Must-Have Skills:

7 10 years of hands-on experience in SoC DFT.

Strong expertise in Scan, ATPG, MBIST.

Experience with pre-silicon validation and post-silicon debug.

Strong problem-solving and debugging skills.

Ability to work effectively in a cross-functional engineering environment.

Skills:

SoC-level DFT architecture , Scan ATPG, MBIST, BSCAN

Job Location:

Bengaluru

Experience:

7 - 10 Yrs

Company Name:

EDA Semiconductor RD

Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

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