- Solid understanding of layouts with process nodes ranging from 40nm,28nm,22nm and FINFET is must.
- Expertise in Cadence XL / VXL and Mentor Graphic Calibre DRC / LVS/Antenna Star-RCXT is must.
- Typically requires more than 5+ years of experience in analog / mixed-signal layout design of deep sub-micron CMOS / FinFET circuits.
1) Analog Layout Engineer - [ID 007]
Typically requires more than 5+ years of experience in analog/mixed-signal layout design of deep sub-micron CMOS/FinFET circuits.
Solid understanding of layouts with process nodes ranging from 40nm, 28nm, 22nm and FINFET is must.
Expertise in layout techniques for managing cross talk, high speed signals, minimizing parasitic, IR drop, EM, RC delays and high-power routing.
Understanding the layout requirement for ESD(HBM/clamps), EOS and latch up technique is must.
Understanding of Analog Layout techniques for LOD/STI, WPE, PSE,
OSE concept is must.
Should be involved in finalizing the bump out/floorplan in discussing with package engineer and cross function teams.
Should be involved in multiple TO s and post TO producer understanding.
Expertise in Cadence XL/VXL and Mentor Graphic Calibre DRC/LVS/Antenna Star-RCXT is must.
Scripting skills for layout automation is a plus.
Skills:
FinFet, CMOS
Job Location:
Bangalore
Experience:
5 - 15 Years
Company Name:
Semiconductor R&D;
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
📌 Analog Layout Engineer (Bengaluru)
🏢 Vitestork Consulting
📍 Bengaluru
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