Job DescriptionPosition Overview: We are seeking a highly skilled and experienced Staff Engineer for our Static Timing Analysis (STA) function. The successful candidate will be part to a team of talented engineers responsible for ensuring the timing performance and integrity of our complex semiconductor designs. This role requires a deep understanding of STA methodologies, leadership skills, and a strategic vision to drive continuous improvement in our timing analysis processes. Key Responsibilities: - Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis. - Work with IP & Design team for Timing constraints Development & Review activities. - Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs. - Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance.
- Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes. - Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance. - Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow. - Prepare and present detailed timing reports and technical documentation to stakeholders - Foster a culture of innovation, collaboration, and continuous improvement within the STA team. Qualifications - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - A minimum of 5 years of experience in Static Timing Analysis. - Proven track record of successfully executing STA - In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus , Constraints Manager) and methodologies. - Robust understanding of digi