We are looking for an energetic passionate and process oriented DFT Engineers Leads who has extensive experience in planning implementation and verification of DFT features for multiple SoC Direct Responsibilities of the role but not limited to working on various aspects of IP and SoC DFT including the DFT Architecture Spyglass DFT RTL implementation Verification Scan and ATPG SCAN insertion ATPG and pattern simulation debug MBIST and Repair implementation and verification TOP DFT architecture Design ATE vector setup and Yield improvement The candidate must be able to drive the DFT implementation for various features including Scan MBIST TAP etc and should have executed at-least 3 full SoC end to end as a DFT engineer Qualifications Bachelor s in Electrical Computer Engineering Computer Science or related field plus 10 years of relevant experience OR a Master s degree in Electrical Computer Engineering Computer Science or related field with 8 years of relevant experience Solid experience of ATPG background Good experience into SCAN related process Previous experience of working with manufacturing engineering on pattern delivery post-silicon support are definite plus Previous experience of working with manufacturing engineering on pattern delivery post-silicon support are definite plus Previous experience of architecting the DFT for multiple SoCs leading team members and Signing off DFT for multiple SoCs

📌 Urgently Hiring 10 + Years Of Dft Lead Engineers Exposure On Scan Insertion, Atpg And Pattern Simulation/debug. Bangalore Location Ctc 80 Lpa+ (Bengaluru)
🏢 Angel u0026 Genie
📍 Bengaluru