06 Aug
|
Chiparama
|
India
Formal Verification Engineer
Location India/USA
Job Description:
Must have a minimum of 10+ years of experience.
We are looking for formal verification experts to ensure design correctness using mathematical verification techniques and advanced formal tools.
Key Responsibilities:
Develop formal verification strategies and methodologies
Write SystemVerilog Assertions (SVA)
Perform property checking, equivalence checking, and CDC/RDC analysis
Identify corner cases missed in simulation
Collaborate with RTL teams for design improvements
Required Skills:
Strong knowledge of formal verification tools (Jasper, VC Formal, etc.)
Expertise in SVA and property specification
Solid understanding of digital design and logic reasoning
Positive to Have:
Experience in low-power/CDC verification
Exposure to security verification
📌 Formal Verification Engineer (India)
🏢 Chiparama
📍 India