Build your career with Sykatiya Technologies

Sykatiya Technologies, believes in Technical Ability along with the Attitude of our highly talented team and reflects the same in the contributions to the customers’ project. Team comprises highly talented engineers and experts from Design Verification, DFT/Test, Physical Design and Analog Design for ASICs.

Back end STA/Synthesis

Experience: 3-12 Years

Location: Bangalore

- 5-12 years of experience in ASIC Physical synthesis/STA
- Expertise in Synopsys/Cadence Synthesis tools
- Expertise with STA with prime time/Tempus.
- Positive Experience in synthesis timing closure and interactions with DFT and PD.
- Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
- Experience in formal verification with Cadence LEC
- Expertise in ECO flows using conformal/Formality ECO.
- Experience in Spyglass Lint/CDC checks and waiver creation
- Experience in RTL HDL languages Verilog/VHDL.
- Understanding of RTL to GDS flow
- Expertise in Perl, TCL language

📌 Back end STA/Synthesis (India)
🏢 Sykatiya Technologies
📍 India