Job Description

Job Summary:

We are seeking a highly experienced Verification Lead to drive the verification strategy and execution for next-generation UA Link Switch products within the Memory Interface Division (MID). The candidate will be responsible for leading verification efforts across complex digital subsystems and SoCs, ensuring first-silicon success for high-performance, high-bandwidth interconnect and switching solutions.

The ideal candidate will possess deep expertise in up-to-date verification methodologies and extensive experience verifying large-scale, high-speed digital designs involving switching fabrics, SerDes-based interfaces, memory subsystems, and complex SoC architectures.

Key Responsibilities

- Define and own the verification strategy, methodology, and execution plan for UA Link Switch products.
- Lead verification architecture, testbench development, coverage planning, and verification closure activities.




- Build and drive scalable UVM/ System Verilog-based verification environments for complex SoC and subsystem designs.
- Collaborate closely with architecture, design, firmware, system validation, and silicon bring-up teams to ensure comprehensive verification coverage.
- Develop verification plans covering functionality, performance, reliability, error handling, and corner-case scenarios.
- Drive debug and root-cause analysis of design and verification issues.
- Define and track verification metrics including functional coverage, code coverage, assertions, and regression quality.
- Lead verification reviews, sign-off activities, and silicon readiness assessments.
- Mentor verification engineers and establish best practices across the organization.

📌 Principal Engineer- Design Verification (Bengaluru)
🏢 renesas electronics
📍 Bengaluru