As a Principal Physical Design engineer, the candidate will be supervised by a local manager, engaging into projects to perform layout floorplanning all the way to GDS convergence and ensure the design is implemented correctly with various checks/verification/audit. He/she will be involved and drive design flow/methodology definition and development to ensure the design team is always using best-in-class design methodology.

Responsibilities

Understand design data flow and complexity, translating to physical design constraints and strategy for convergence with best PPA metrices.

Strategize floor-planning options and experimentation, fine tune Place & Route for design specific needs and close timing requirement within given power envelope.

Implement Low Power physical design flows and methodologies such as Power-Gating, Clock-Gating and MBR flows.

Perform and debug LEC in ensuring design equivalence against synthesized gate-level netlist.

Guiding/leading junior members of the team with effective coaching approach.

Enhance tools, flows and methodologies to meet design TAT

Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule

Requirements/Qualifications

Qualifications: This position requires at least BSEE with 6-10 years of ASIC development experience in a rapid paced environment.



You are required to have expertise in a wide range of areas in design, tools and flows:

BEng/MEng in EE or equivalent with the completion of several complexes ASIC or IC tapeouts in VDSM process technology nodes.

Experience taking large blocks to timing, physical design and DRC/LVS closure.

Experience in physical design with the understanding of VDSM effects and issues with excellent debugging and analytical skills.

Understand floor planning, placement and optimization for timing closure, clock network planning, power distribution planning and routing.

Experienced in main P&R; tools such as Synopsys ICC/PT, Cadence Innovus and ETS.

Post layout physical verification and DFM rules (Cadence PVS).

Understand Low Power methodology, Static Timing Analysis, Signal/Power Integrity to meet design goals.

Experienced in scripting (TCL, PERL & Shell) and working knowledge of HDL (Verilog, VHDL) with solid understanding of UNIX/LINUX.

Knowledge of synthesis tools (e.g. Design compiler, Genus or equivalent) and static timing analysis tools (e.g.

Prime

Time or equivalent) is a plus.

Excellent verbal and written communication skills. Strong interpersonal skills.

Ability to lead and mentor others and work under challenging environment Exp : 5+Years

Notice period : Immediate to 30 days

📌 Physical Design Engineer (Bengaluru)
🏢 VNC Digital Services
📍 Bengaluru