Hi,
Please find the JD below:-
10+ years experience in Intel/Altera FPGAs (Agilex, Stratix‑10, Arria‑10) • Architecting FPGA systems with PCIe Gen4/Gen5 Hard IP • Expertise in Quartus Prime Pro, Platform Designer, timing closure, transceiver configuration • Experience with NVMe/PCIe protocols, DMA engines, and high‑speed digital design • Ownership of system architecture, FPGA design reviews, floorplanning, and integration • Guide team on RTL quality, CDC, SDC constraints, SignalTap debug, and performance optimization.
Kindly note: Altera FPGA and PCIe Gen 3/4/5 experience is mandatory.
Please do share your resume to
[email protected] or refer your friends or colleagues.
Regards,
Jaya
📌 Opening for FPGA Design - Bangalore (Bengaluru)
🏢 UST
📍 Bengaluru