Job Title: DFX Timing Engineer - 5-6 Yrs

Location: Bangalore

No. Of positions: 1

Experience required: 5-6 Years

The Role:

As a contract member of the SoC DFT team, the candidate will support DFT timing closure and sign-off for complex SoCs. The role focuses on developing and validating DFT timing constraints, debugging timing issues, and working with DFT, Design, and Physical Design teams to ensure clean test-mode timing closure.

Key Responsibilities:

- Develop and validate DFT timing constraints for Scan, ATPG, and MBIST modes.
- Perform block-level and top-level STA analysis for DFT/test modes.
- Support DFT timing closure and sign-off activities.
- Debug and resolve DFT-related timing and constraint issues with Design and Physical Design teams.
- Develop or improve automation scripts to increase DFT timing productivity.

Required / Preferred Experience:

- 5+ years of experience in DFT, STA,



or SoC timing closure.
- Hands-on experience with DFT constraints, timing closure, and sign-off flows.
- Valuable understanding of Scan, ATPG, MBIST, and DFT methodologies.
- Experience with RTL quality check tools such as SpyGlass, CDC, Lint, or similar tools.
- Strong debug skills and scripting ability in TCL, Perl, Python, or Shell.

Qualification:

- B.E./B.Tech/M.E./M.Tech in Electrical, Electronics, or related engineering discipline.

Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 DFX Timing Engineer (Bengaluru)
🏢 Proxelera
📍 Bengaluru