06 Aug
|
Mirafra
|
Bengaluru
- Experience in debugging LVS issues at chip-level with complex analog-mixed signal Ips.
- Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.)
- Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components
Experience (years) : 4+ years
Education Qualification:
BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent
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📌 Physical Verification professional (Bengaluru)
🏢 Mirafra
📍 Bengaluru