Memory Layout Engineer (Bengaluru)

Memory Layout Engineer (Bengaluru)

06 Aug
|
Leadic Design
|
Bengaluru

06 Aug

Leadic Design

Bengaluru

Memory Layout Engineers
Location : Bangalore.
Experience in custom/analog memory layout, SRAM/compiler layout, Cadence Virtuoso, DRC/LVS & advanced nodes preferred.
Notice Period : Immediate to 15-day joiners only.

📌 Memory Layout Engineer (Bengaluru)
🏢 Leadic Design
📍 Bengaluru

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