- Design, develop, and execute verification plans for complex digital circuits using ATPG, DFT, and RTL techniques.
- Collaborate with cross-functional teams to identify and resolve issues related to chip design, integration, and testing.
- Develop and maintain testbenches for SoCs (Systems on Chip) using SystemVerilog/UVM methodology.
- Analyze results from simulation runs to identify defects in the design.
Job Requirements :
- 11-18 years of experience in Verification Engineering with expertise in ATPG, DFT, RTL languages like VHDL or Verilog.
- Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
- Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
- Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
- Experience working on high-speed interfaces such as Ethernet MACs/PHYs or similar technologies.