Design Engineer I At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

What we are looking for : Minimum Qualifications:

- 2-10 years (with Btech) or 8 years (with Mtech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
- 2-3 years of management experience leading/mentoring a small team of engineers • Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on PCIe/CXL/UCIe/Ethernet.
- Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.

Preferred Qualifications

- Experience leading System testing efforts for SERDES solutions.
- Experience in PCIe/UCIe LTSSM states is a plus.
- 1-2 years of experience in FPGA Design and Schematic design.
- 1-2 years of IP/SoC Physical Layer Electrical Validation experience is a plus.
- Familiarity with Verilog RTL coding for FPGA, python,C/C++ • Valuable communication skills We’re doing work that matters. Help us solve what others can’t.

Experience Level Senior Level

📌 Design Engineer - Physical Layer and System Testing (Bengaluru)
🏢 Cadence Design Systems (India
📍 Bengaluru