Role Description

- Should have led Physical Design execution of low-power, multiple voltage/power domain based SoC

- Should be able to handle Die-size estimation, IO/ESD/package planning, Floorplan, power plan

- Should be able to drive Synthesis, P&R;, timing, Physical Verification and IR/EM convergence

- Should be able to handle LP-aware synthesis of SoC, tweak the flow to meet PPA targets

- Should be able to debug and resolve RTL2N LEC, N2N, LP-LEC issues

- Should be able to run CLP and resolve gate level CLP violations

- Familiarity with Multi-voltage, multi-power domain based Low power implementation

- Expected to handle constraints bring-up for Func/DFT/IO modes

- Should have valuable constraints debug and validation skills

- Should be familiar with timing closure at various stages (preLayout, postLayout)

- Familiarity with Multi-voltage, multi-power domain based STA

- Should be able to handle P&R; of SoC Top





- Should be able to customize the PNR flow to meet PPA and low power requirements

- Should be able to resolve timing/congestion issues

- Should have worked on Multi-voltage, multi-power domain based designs

- Should be able to handle power grid development using tool automation and custom scripts

- Should have handled SoC level EM/IR analysis (Static, Dynamic IR, power/signal EM) for SoC with power switches

- Should be able to analyse, root-cause and fix IRdrop issues

- Should be familiar with custom placement/routing using semi-automatic/manual method

- Should have worked on Physical Verification checks for Low Power SoC (DRC, ERC, LVS, ANT, ESD, DFM)

Skills vlsi design,physical design,floorplan,timing analysis,

📌 Associate III - VLSI PD PnR (Bengaluru)
🏢 UST
📍 Bengaluru