06 Aug
|
VMware
|
Bengaluru
Mandatory Requirements:
+ BS/BE degree in Engineering.
+ More than 10 years of experience writing and debugging test benches
+ Must have deep understand of full ASIC cycle, right from conceptualization to TapeOut.
+ Must have proficiency in constrained random verification methodologies like UVM/VMM/OVM
+ Must be proficient with System Verilog
+ Should have exceptionally valuable command over fundamental OOP principles.
+ Should be open to learning verification methodologies and strategies, that may be cutting edge but different from the industry standard.
+ Motivated and self-driven.
📌 ASIC Verification (Bengaluru)
🏢 VMware
📍 Bengaluru