Key Skills and Responsibilities:

- 10 to 15 years of experience in SoC/IP Design.
- Should have solid experience in very large SoC Integration in a highly complex Front-end environment
- Should have worked on at least 2 SoC integration project completing RTL freeze
- Able to analyse/define/develop/write micro-Architecture specification for a sub-system
- Interact with Architect/stakeholders and understand the Module/Sub-system requirements
- Should be able to own and drive Quality check of the sub-system (CDC, RDC, Lint, DFT Lint) and take to closure
- Able to write glue logic/gasket/bridge modules as required
- Should have solid experience in working with teams across multiple time zones
- Experience in working large SoC/Chiplet design . Designs with Multi Clock/Reset/Voltage and Power domain




- Able to review and provide timing constraints at sub-system level. Need to co-ordinate with implementation team
- Experience in High-speed protocol based sub-system like PCIE SS, Ethernet SS, LPDDR is a most preferred
- Need to be self-driven and committed.
- Need to be agile, delivering results in a agile SoC development
- Need to be adept in finding design solution at SoC level

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Sr. Design Lead (Chennai)
🏢 TESSOLVE
📍 Chennai