Physical Design Engineer | 3 To 8 Years | Bangalore

Company: Corp Match Pvt. Ltd.
Location: Bangalore|Hyderabad
Experience: 3 To 8 Years
Employment Type: Full Time
Work Mode: Onsite

About the Role

We are hiring experienced Physical Design Engineers for one of our leading semiconductor clients. The ideal candidate should have strong expertise in the complete Physical Design flow from floorplanning to signoff.

Roles & Responsibilities

- Work on complete ASIC Physical Design implementation.
- Perform Floorplanning, Placement, CTS, Routing, and Physical Verification.
- Execute Timing Closure and Static Timing Analysis (STA).
- Perform Power Analysis, IR Drop, and EMIR analysis.
- Handle Synthesis and Logic Equivalence Check (LEC).
- Collaborate with RTL, DFT, and Signoff teams.
- Debug timing, congestion, and power-related issues.
- Ensure design quality and meet project schedules.

Required Skills

- Physical Design
- Floorplanning
- Placement
- Clock Tree Synthesis (CTS)
- Routing
- Timing Closure




- Static Timing Analysis (STA)
- Physical Verification (PV)
- DRC/LVS
- Synthesis
- Logic Equivalence Check (LEC)
- EMIR / IR Drop Analysis

Tools

Experience with one or more of the following:

- Synopsys ICC2
- Cadence Innovus
- Synopsys PrimeTime
- Cadence Tempus
- Synopsys Design Compiler
- Cadence Genus
- Synopsys Formality
- Cadence Conformal
- Calibre
- RedHawk
- Voltus

Qualifications

- 2023 B.E./B.Tech/M.E./2025/2026 M.Tech in ECE, EEE, VLSI, Electronics, or related discipline.

Preferred

- Experience with advanced technology nodes (16nm/7nm/5nm/3nm).
- Knowledge of Low Power Design (UPF/CPF).
- Positive debugging and problem-solving skills.
- Excellent communication skills.

Location

Bangalore | Hyderabad

Notice Period

Immediate to 30 Days Preferred

Interested Candidates

Share your updated resume to:

[email protected]
+91 78427 70474

📌 Physical Design Engineer -PV -STA-EMIR (Hyderabad)
🏢 Corp Match
📍 Hyderabad