POSITION SUMMARY

The candidate should have direct and first-hand experience working in managing 4 -10 member engineering team – and servicing clients in Project (ODC) based execution model as well as Staffing (Hyderabad Onsite requirements).

ROLE & RESPONSIBILITIES

Incumbent will be responsible for Architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to various customers products

Incumbent will lead of an IP Verification team and provide technical leadership to the Design Verification team as a whole

To lead a team of 10-13 engineers

Effectively manage team members through coaching and mentoring and provide guidance and career planning to team-members.

Must lead management and customer reviews for multiple projects

The specification, implementation, and maintenance of an integrated end-to-end formal verification flow for the formal verification objective.

Develop/modify scripts to automate the verification process.

Maintain and extend assertion libraries, including support for both simulation and FV.

Developing verification environment including workplace assumptions, assertions, and cover properties in context of the verification plan

ESSENTIAL SKILLS & EXPERIENCE





Minimum 6 years of experience in System Verilog HVL.

Minimum 6 year of experience in OVM/UVM/VMM/Test Harness.

Hands on experience of developing assertion, checkers, coverage and scenario creation.

Must have executed at-least 2 to 3 SoC Verification projects

Experience in developing test and coverage plan, Verification environment and validation plan.

Knowledge of at-least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required.

Review and Audit participation.

At-least 3 years of experience in handling team of 5 to 10 engineers.

Define/derive Scope, Estimation, Schedule and Deliverables of proposed work.

Assure compatibility of resources, tools, platform

Work with customers through acceptance of deliverables.

Effectively manage team members through coaching and mentoring and provide guidance and career planning to team-members.

Please note that this is a Work from Office Job and incumbent must have willingness and experience of leading and mentoring junior engineers.

EDUCATION BACKGROUND

B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.

📌 ASIC Design Verification Lead (Hyderabad)
🏢 Einfochips
📍 Hyderabad