Job Title: DV Engineer (SV UVM) - 2-3 Yrs

Client: AMD Xilinx

Location: Hyderabad

No. Of positions: 1

Experience required: 2-3 Yrs

JOB DUTIES:

- Participate in the functional verification of a block(s) of complex ASICs and/or IP cores.
- Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation.
- Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.
- Be familiar with hardware modelling and/or assertion-based verification methods.

EXPERIENCE AND EDUCATION:





- 2-3 years of proven verification experience on large ASIC development projects experience in a hardware development setting; Strong background in SV/UVM, C, Regression management, SPI, I2C, UART, Ethernet, PCIe Protocol Knowledge, ARM Processor architecture knowledge in a Linux Environment; Robust debug skills and experience with debug tools such as VCS, Verdi; Proficient in Make files; Experience in Verilog/System Verilog/System C, preferred; Strong analytical skills and attention to detail; Excellent written and communication skills

Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

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