Job Title: ASIC/RTL Design Engineer - 8-10 Yrs

Location: Bangalore

No. Of positions: 1

Experience required: 8-10+ years

THE ROLE:

- The focus of this role will involve driving the physical design flow from timing through final sign-off, collaborating closely with cross-functional teams to meet stringent power, performance, and area (PPA) targets on SerDes PHY IPs.

THE PERSON:

- As a senior member of the SerDes IP Physical Design team, you will handle static timing analysis (STA) of critical paths. Your main focus will be ensuring timed paths are clean, understood, and communicated to the PD/RTL/Architecture team. Identify creative solutions for complex paths in multi-mode, functional, and test scenarios. This role requires deep technical expertise in physical design tools and methodologies and the ability to lead and mentor physical design engineers.

KEY RESPONSIBILITIES:

- Lead and develop timing methodologies, establish SDC constraints, and automate processes for special timing checks, ensuring design convergence and managing ECOs effectively.
- Perform static timing analysis setup and sign-off for multi-corner, multi-voltage processes to align with PPA targets, initially at the hierarchical level and subsequently at the top-level, reviewing the timing arcs for the .lib generation.
- Collaborate closely with RTL, DFT, and IP teams to ensure smooth integration and address physical design concerns affecting scan shift and scan capture modes for test.
- Identify opportunities to optimize clock skew and insertion delay across various corners and modes.
- Evaluate the clock/reset-domain-crossing (CDC/RDC)



issues at the netlisting stage and offer feedback on design fixes or establish waivers if the changes are not feasible.
- GateCDC/GCA Analysis and waivers
- Implement power-saving strategies, such as power gating, multi-voltage domains, and clock gating, to meet low-power objectives while preserving performance standards.
- Create and refine custom scripts using Tcl, Perl, or Python to enhance workflow efficiency and streamline physical design operations.
- Mentor and support junior physical design engineers, disseminating best practices and providing technical guidance to elevate team proficiency and performance.

PREFERRED EXPERIENCE:

- Over 8-10+ years of professional experience in constraints generation, synthesis, static timing analysis (STA), and IP-level timing and physical design, with a preference for high-performance SerDes designs.
- Proven ability in timing analysis, convergence, timing ECOs, and .lib generation.
- Experience with STA closure on PHYs understanding the timing requirements across digital and analog macro interfaces is a plus.
- Proficient in physical design tools such as Synopsys ICC2, Primetime, and the ASIC design flow.
- Skilled in scripting with Tcl, Python, or Perl to automate and streamline physical design tasks.
- Excellent problem-solving, leadership, and communication skills and values team culture.
- Capable of thriving in rapid-paced environments and managing multiple projects simultaneously.

ACADEMIC CREDENTIALS:

- Master s degree in computer engineering/electrical engineering

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 ASIC/RTL Design Engineer (Bengaluru)
🏢 Proxelera
📍 Bengaluru